By Himanshu Bhatnagar
Complicated ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complex techniques and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the complete ASIC layout circulation method certain for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time program of Synopsys instruments, used to wrestle a number of difficulties noticeable at VDSM geometries. Readers can be uncovered to an efficient layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties with regards to every one part of the layout movement are pointed out, with strategies and work-around defined intimately. furthermore, the most important concerns regarding format, consisting of clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the e-book includes in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, particular in the direction of optimum synthesis resolution. objective audiences for this ebook are practising ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT thoughts.
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Additional info for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
There are tools available in the market that may be used to generate the BIST controller and surrounding logic. Unfortunately, Synopsys does not provide this capability. The scan insertion may be performed using the test ready compile feature of DC. This procedure maps the RTL directly to scan-flops, before linking them in a scan-chain. An advantage of using this feature is its ability to enable DC to take the scan-flop timing into account while synthesizing. This technique is important since the scan-flops generally have different delays associated with them as compared to their non-scan equivalent flops (or normal flops).
This design contains a single 30 MHz clock called “tck” and a reset called “trst”. Timing specifications for this design dictate that the setup-time needed for all input TUTORIAL 21 signals with respect to “tck” is 10ns, while the hold-time is 0ns. Furthermore, all output signals must be delayed by 10ns with respect to the clock. 25 micron. In order to achieve greater accuracy due of variance in process, two Synopsys standard cell technology libraries, characterized for worst-case and the best-case process parameters are used.
This process is termed as synthesis. ASIC DESIGN METHODOLOGY 7 Synopsys's Design Compiler (from now on termed as, DC) is the de-facto standard and by far the most popular synthesis tool in the ASIC industry today. Synthesizing a design is an iterative process and begins with defining timing constraints for each block of the design. These timing constraints define the relationship of each signal with respect to the clock input for a particular block. In addition to the constraints, a file defining the synthesis environment is also needed.
Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime by Himanshu Bhatnagar